// (C) Copyright 2012 Kystar. All rights reserved.

`timescale 1ns/100ps
`default_nettype none

module spi_top
(
    input  wire I_sclk,
    input  wire I_rst_n,

    //--------------------------------------------------------------------
    // spi
    //--------------------------------------------------------------------
    input  wire I_mcu_clk,
    input  wire I_mcu_cs,
    input  wire I_mcu_dat_in,
    output wire O_mcu_dat_out,

    //--------------------------------------------------------------------
    // write
    //--------------------------------------------------------------------
    output wire          O_action_wren,
    output wire          O_cfg_wren,
    output wire          O_edid_ram_wren,
    output wire [  3: 0] O_px_pkg_ram_wren,
    output wire [ 11: 0] O_waddr,
    output wire [  7: 0] O_wdata,

    //--------------------------------------------------------------------
    // read 
    //--------------------------------------------------------------------
    output wire [ 11: 0] O_raddr,
    //
    output wire          O_status_rden,
    input  wire [  7: 0] I_status_rdata,
    //
    output wire          O_action_rden,
    input  wire [  7: 0] I_action_rdata,
    //
    output wire          O_cfg_rden,
    input  wire [  7: 0] I_cfg_rdata,
    //
    output wire          O_edid_ram_rden,
    input  wire [  7: 0] I_edid_ram_rdata,
    //
    output wire [  3: 0] O_px_pkg_ram_rden,
    input  wire [  7: 0] I_p0_pkg_ram_rdata,
    input  wire [  7: 0] I_p1_pkg_ram_rdata,
    input  wire [  7: 0] I_p2_pkg_ram_rdata,
    input  wire [  7: 0] I_p3_pkg_ram_rdata,
    //
    output wire [  3: 0] O_px_comm_back_ram_rden,
    input  wire [  7: 0] I_p0_comm_back_ram_rdata,
    input  wire [  7: 0] I_p1_comm_back_ram_rdata,
    input  wire [  7: 0] I_p2_comm_back_ram_rdata,
    input  wire [  7: 0] I_p3_comm_back_ram_rdata

);

/******************************************************************************
                                <localparams>
******************************************************************************/

/******************************************************************************
                              <internal signals>
******************************************************************************/
wire       clk_posedge;
wire       dat_begin;
wire       datin_valid;
wire [7:0] datin;
wire       datout_valid;
wire [7:0] datout;

/******************************************************************************
                                <module body>
******************************************************************************/
mcu_rx u_mcu_rx
(
    .reset_n      (I_rst_n),
    .sysclk       (I_sclk),

    .mcu_clk      (I_mcu_clk),
    .mcu_cs       (I_mcu_cs),
    .mcu_dat_in   (I_mcu_dat_in),

    .clk_posedge  (clk_posedge),
    .dat_begin    (dat_begin),
    .datin_valid  (datin_valid),
    .datin        (datin)
);

mcu_tx u_mcu_tx
(
    .reset_n      (I_rst_n),
    .sysclk       (I_sclk),
    .clk_posedge  (clk_posedge),

    .datout_valid (datout_valid),
    .datout       (datout),

    .mcu_dat_out  (O_mcu_dat_out)
);

mcu_decode u_mcu_decode
(
    .I_rst_n(I_rst_n),
    .I_sclk(I_sclk),

    .I_clk_posedge(clk_posedge),
    .I_dat_begin(dat_begin),
    .I_datin_valid(datin_valid),
    .I_datin(datin),

    .O_datout_valid(datout_valid),
    .O_datout(datout),
    //       
    .O_action_wren(O_action_wren),
    .O_cfg_wren(O_cfg_wren),
    .O_edid_ram_wren(O_edid_ram_wren),
    .O_px_pkg_ram_wren(O_px_pkg_ram_wren),
    .O_waddr(O_waddr),
    .O_wdata(O_wdata),
    //
    .O_raddr(O_raddr),
    //
    .O_status_rden(O_status_rden),
    .I_status_rdata(I_status_rdata),
    //
    .O_action_rden(O_action_rden),
    .I_action_rdata(I_action_rdata),
    //
    .O_cfg_rden(O_cfg_rden),
    .I_cfg_rdata(I_cfg_rdata),
    //
    .O_edid_ram_rden(O_edid_ram_rden),
    .I_edid_ram_rdata(I_edid_ram_rdata),
    //
    .O_px_pkg_ram_rden(O_px_pkg_ram_rden),
    .I_p0_pkg_ram_rdata(I_p0_pkg_ram_rdata),
    .I_p1_pkg_ram_rdata(I_p1_pkg_ram_rdata),
    .I_p2_pkg_ram_rdata(I_p2_pkg_ram_rdata),
    .I_p3_pkg_ram_rdata(I_p3_pkg_ram_rdata),
    //
    .O_px_comm_back_ram_rden(O_px_comm_back_ram_rden),
    .I_p0_comm_back_ram_rdata(I_p0_comm_back_ram_rdata),
    .I_p1_comm_back_ram_rdata(I_p1_comm_back_ram_rdata),
    .I_p2_comm_back_ram_rdata(I_p2_comm_back_ram_rdata),
    .I_p3_comm_back_ram_rdata(I_p3_comm_back_ram_rdata)
);

endmodule
`default_nettype wire
